1. Field
This disclosure relates generally to detecting an imminent read failure in a memory array and, more specifically, to time-based techniques for detecting an imminent read failure in a memory array.
2. Related Art
A soft memory error (e.g., attributable to electrical or magnetic interference) can cause one or more memory (bit) cells of a random access memory (RAM) module of a computer system to spontaneously flip to a non-written state. The majority of soft errors in RAM modules occur as a result of background radiation that changes the contents of one or more bit cells, or interferes with circuitry used to read/write the bit cells. Soft errors may be mitigated by using RAM modules that include extra memory bits and memory controllers that exploit the extra memory bits. The extra bits may be used to record parity or implement an error correcting code (ECC). Similarly, hard errors (i.e., errors that are not transient) in RAM modules may also be corrected using ECC. In general, parity allows for the detection of a single-bit error. Hamming code, which is one of the most commonly implemented ECCs, allows a single-bit error to be detected and corrected and (in the usual configuration, with an extra parity bit) double-bit errors to be detected (but not corrected). Various memory controllers are designed to support ECC. However, motherboards employed in low-cost computer systems typically do not support ECC. Most low-cost ECC-capable memory controllers only detect and correct single-bit errors of a word, e.g., a 64-bit word, and detect (but not correct) errors of two bits per word. For example, an ECC word checkbase for a 64-bit word may include seventy-two bits (i.e., sixty-four natural bits and eight parity bits). Other ECC-capable memory controllers are capable of detecting and correcting multiple bits per word.
The basic input/output system (BIOS) in some computer systems, as well as some operating systems (OSs), e.g., Linux, allow for counting of detected and corrected memory errors, in part to help identify failing memory modules before a problem becomes catastrophic (i.e., before memory errors become uncorrectable). Error detection and correction depends on an expectation of the kinds of errors that occur. As long as the number of bits in any particular word does not exceed the number of bits that an implemented ECC can correct, a memory system presents the illusion of an error-free memory system.
ECC has also been employed in non-volatile memory (NVM) applications. For example, embedded NVM (eNVM) employed in automotive applications has implemented ECC to correct read failures. In general, a read failure occurs when what was programmed into a bit cell (data or code) is not read out of the bit cell. For example, in a typical NVM (e.g., a Flash memory) a digital one and a digital zero in a bit cell are indicated by a different charge. For example, a cell that is charged may indicate a digital zero and a cell that is not charged may indicated a digital one. An NVM bit cell can gain or lose electrons if the bit cell is defective. In a typical NVM, a bit cell error is a hard error. That is, in a typical NVM, a bit cell that gains electrons will not subsequently lose electrons. Similarly, in a typical NVM, a bit cell that loses electrons will not subsequently gain electrons.